LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;


entity regmem is
  port ( 
    CLK							     :		 in	std_logic;
    nReset         :   in std_logic;
    memen           :   in std_logic;
    memPC4          :   in std_logic_vector (31 downto 0);    
    memDMEM_out     :  in std_logic_vector(31 downto 0);
    memALU_out      :  in std_logic_vector(31 downto 0);
    memRd     :  in std_logic_vector(4 downto 0);
    memWBctrl       :  in std_logic_vector(3 downto 0);
    memImmExtend    :  in std_logic_vector(31 downto 0);
    memhalt         :  in std_logic;
    
    wbDMEM_out     :  out std_logic_vector(31 downto 0);
    wbALU_out      :  out std_logic_vector(31 downto 0);
    wbRd     :  out std_logic_vector(4 downto 0);
    WBctrl         :  out std_logic_vector(3 downto 0);
    wbImmExtend    :  out std_logic_vector(31 downto 0);
    wbhalt         :  out std_logic;
    wbPC4          :   out std_logic_vector (31 downto 0)
  );
end regmem;

architecture arch of regmem is
  signal q0, n0  : std_logic_vector (31 downto 0);
  signal q1, n1  : std_logic_vector (31 downto 0);
  signal q2, n2  : std_logic_vector (4 downto 0);
  signal q3, n3  : std_logic_vector (3 downto 0);
  signal q4, n4  : std_logic;
  signal q5, n5  : std_logic_vector(31 downto 0);
  signal q6, n6  : std_logic_vector(31 downto 0);
    
begin
  
  proc : process(CLK,nReset)
  begin
    if (nReset = '0')  then
      q0 <= x"00000000";
      q1 <= x"00000000";
      q2 <= (others => '0');
      q3 <= (others => '0');
      q4 <= '0';
      q5 <= (others => '0');
      q6 <= (others => '0');
    elsif rising_edge(CLK) then
      q0 <= n0;
      q1 <= n1;
      q2 <= n2;
      q3 <= n3;
      q4 <= n4;
      q5 <= n5;
      q6 <= n6;

    end if;
  end process proc;

  n0 <= memDMEM_out when memen = '1' else
        q0 when memen = '0' else
        x"00000000";
  n1 <= memALU_out when memen = '1' else
        q1 when memen = '0' else
        x"00000000";
  n2 <= memRd when memen = '1' else
        q2 when memen = '0' else
        (others => '0');
  n3 <= memWBctrl when memen = '1' else
        q3 when memen = '0' else
        (others => '0');
        
  n4 <= memhalt when memen = '1' else
        q4 when memen = '0' else
        '0';  
  n5 <= memImmExtend when memen = '1' else
        q5 when memen = '0' else
        (others => '0');

  n6 <= memPC4 when memen = '1' else
        q6 when memen = '0' else
        (others => '0');

  wbDMEM_out            <= q0;
  wbALU_out      <= q1;
  wbRd      <= q2;
  WBctrl             <= q3;
  wbhalt          <= q4;
  wbImmExtend     <= q5;
  wbPC4           <= q6;

  
     
end arch;